The present invention generally relates to computer-aided circuit design systems and, more particularly, to a method and apparatus for evaluating the design quality of a network of nodes in an integrated circuit to determine the effective wire resistance at a receiver node of the network.
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components comprised on a single semiconductor xe2x80x9cchipxe2x80x9d in which the components are interconnected to perform a given function. Typical examples of integrated circuits include, for example, microprocessors, programmable logic devices (PLDs), electrically erasable programmable memory devices (EEPROMs), random access memory devices (RAMs), operational amplifiers and voltage regulators. A circuit designer typically designs the integrated circuit by using very large scale integrated (VLSI) circuit design techniques to create a circuit schematic which indicates the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and to ensure that performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. As will be appreciated by those skilled in the art, electronic devices include electrical analog, digital, mixed hardware, optical, electro-mechanical, and a variety of other electrical devices. The design and the subsequent simulation of any circuit board, VLSI chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today""s sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without having to perform costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools must deal with an electronic representation of the hardware device. A xe2x80x9cnetlistxe2x80x9d is one common representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a xe2x80x9cnetlistxe2x80x9d is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often, a netlist will contain a number of circuit xe2x80x9cmodulesxe2x80x9d which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by xe2x80x9cblack boxes.xe2x80x9d As will be appreciated by those skilled in the art, a black box is a system or component whose inputs, outputs, and general function are known, but whose contents are not shown. These xe2x80x9cblack boxxe2x80x9d representations, hereinafter called xe2x80x9cmodulesxe2x80x9d, will mask the complexities therein, typically showing only input/output ports.
An integrated circuit design can be represented at different levels of abstraction, such as the Register-Transfer level (RTL) and the logic level, using a hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an integrated circuit design is specified using behavioral or structural descriptions, or a mix of both. At the logical level, the behavioral description is specified using boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are fill-adders, NAND gates, latches, and D-Flip Flops.
Having set forth some very basic information regarding the representation of integrated circuits and other circuit schematics through netlists, systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems identify certain critical timing paths, and then evaluate the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One such system known in the prior art is marketed under the name PathMill, by EPIC Design Technology, Inc., subsequently purchased by Synopsis, Inc. PathMill is a transistor-based analysis tool used to find critical paths and to verify timing in semiconductor designs. Using static and mixed-level timing analysis, PathMill processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. As is known, PathMill can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the PathMill product and other similar products. One primary shortcoming of the PathMill program is that it does not analyze the circuits to determine the design quality of the circuits. Rather, PathMill performs a static timing analysis of a circuit using the netlist provided to PathMill. Furthermore, configuring PathMill to recognize various circuit characteristics is typically a very difficult task.
Accordingly, a need exists for a rules checking system that will allow circuits to be evaluated for design quality. The present invention works in conjunction with a tool, such as, for example, PathMill, to build a database which is then utilized by the rules checking system of the present invention to evaluate the design quality of network nodes. Typically, such tools, including PathMill, receive a netlist and use the netlist to determine FET (field effect transistor) direction, node types, latches, dynamic gates, rise and fall times, etc. This information is utilized by the present invention to build a database which is then utilized by the rules checking system of the present invention to evaluate the design quality of network nodes, preferably of network nodes of FET-level circuits designed in accordance with VLSI techniques.
In accordance with the present invention, the rules checking system evaluates a network of nodes to determine the effective wire resistance of the network, which is derived from parasitic wire resistances within the network. The parasitic wire resistances result from the conductors that are instantiated in the integrated circuit to create the interconnects between the FETs. The effective wire resistance at a node is needed in order to calculate the cross-capacitance noise at the node.
Integrated circuits can be viewed as a plurality of drivers and receivers with parasitic wire resistances disposed between them. A driver is a gate comprised of a plurality of FETs which drives another gate which is also comprised of a plurality of FETs. The gate being driven is commonly referred to as the receiver. The driver and receiver gates may be, for example, inverters. A receiver node is the node at the input of a receiver. Each conductor that interconnects the output of a driver to the input of a receiver has an individual parasitic resistance associated with it.
The individual parasitic wire resistances between physical nodes may be obtained by an RC extraction program. RC extraction programs are well known in the art and are currently available on the market. The individual parasitic wire resistances may be passed to a timing analyzer program such as Pathmill in the form of a netlist. The timing analyzer program may utilize this information to perform certain types of analyses.
Conventional circuit analysis techniques can be used to calculate the effective wire resistance attributable to the individual parasitic wire resistances. Another technique that can be used to calculate the effective wire resistance of a circuit is to simulate the FETs of the drivers and receivers and then simulate the operation of the circuit using a program such as Spice to calculate the effective wire resistance at the receiver node. One disadvantage of these approaches is that the strengths of the FETs must be determined in order for the effective wire resistance to be determined, which can be a difficult task. It would be advantageous to provide a system for determining the effective wire resistance at a receiver node in an integrated circuit which does not require the calculation of the individual strengths of the FETs of the circuit.
Accordingly, a need exists for a rules checking system which will calculate the effective wire resistance of a receiver node in an integrated circuit and which does not require that the strengths of the FETs of the network be calculated.
The present invention provides a method and apparatus for evaluating an integrated circuit design to determine the effective wire resistance at a receiver node of a receiver gate disposed in a network of the integrated circuit. The rules checker apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to calculate the effective wire resistance at the receiver node. The rules checker of the present invention traverses a path from the output node of a driver gate to the receiver node of the receiver gate and recursively sums the values of the parasitic resistances encountered along the path to maintain a total resistance value. Once the rules checker determines that the receiver node has been reached, the rules checker determines that the total resistance value equals the effective wire resistance at the receiver node.
In accordance with the preferred embodiment of the present invention, the rules checker also is capable of determining whether or not a path being traversed is a false path, i.e., a path that does not lead to the receiver node. When the rules checker determines that a path being traversed does not lead to the receiver node, the total resistance value is set to 0 so that the parasitic resistances along the false path are not taken into account in calculating the effective wire resistance at the receiver node.
When traversing a path, the rules checker processes each node of the network and identifies parasitic resistances connected to the nodes. When the rules checker encounters a parasitic resistance connected to a node, the rules checker determines whether or not the encountered parasitic resistance has previously been marked. If the rules checker determines that the encountered parasitic resistance has not previously been marked, the rules checker marks the encountered parasitic resistance and the node being processed. The rules checker then adds the value of the encountered parasitic resistance to a value of a TOTAL RESISTANCE variable. When the rules checker reaches the receiver node, it determines that the value of the TOTAL RESISTANCE variable is equal to the effective wire resistance at the receiver node.